Target-specific Code

Definitions and functions to support the compilation target. More...

Macros
#define	TARGET_NAME   "RISC-V_RV32IM"
	Name of the target architecture.
#define	TARGET_PTR_GRANULARITY   1
	Number of bytes for each memory address.
#define	TARGET_REG_ZERO_IS_CONST   true
#define	NUM_GP_REGS   23
	Number of general-purpose registers usable by the register allocator.
#define	NUM_SPILL_REGS   3

Typedefs
typedef int32_t	t_regInt
	Signed data type with the same size of a target register.

Enumerations
enum	{   REG_ZERO = 0 , REG_RA , REG_SP , REG_GP ,   REG_TP , REG_T0 , REG_T1 , REG_T2 ,   REG_S0 , REG_S1 , REG_A0 , REG_A1 ,   REG_A2 , REG_A3 , REG_A4 , REG_A5 ,   REG_A6 , REG_A7 , REG_S2 , REG_S3 ,   REG_S4 , REG_S5 , REG_S6 , REG_S7 ,   REG_S8 , REG_S9 , REG_S10 , REG_S11 ,   REG_T3 , REG_T4 , REG_T5 , REG_T6 ,   NUM_REGISTERS }
	Machine register names. More...
enum	{   OPC_ADD , OPC_SUB , OPC_AND , OPC_OR ,   OPC_XOR , OPC_MUL , OPC_DIV , OPC_REM ,   OPC_SLL , OPC_SRL , OPC_SRA , OPC_ADDI ,   OPC_SUBI , OPC_ANDI , OPC_ORI , OPC_XORI ,   OPC_MULI , OPC_DIVI , OPC_REMI , OPC_SLLI ,   OPC_SRLI , OPC_SRAI , OPC_SEQ , OPC_SNE ,   OPC_SLT , OPC_SLTU , OPC_SGE , OPC_SGEU ,   OPC_SGT , OPC_SGTU , OPC_SLE , OPC_SLEU ,   OPC_SEQI , OPC_SNEI , OPC_SLTI , OPC_SLTIU ,   OPC_SGEI , OPC_SGEIU , OPC_SGTI , OPC_SGTIU ,   OPC_SLEI , OPC_SLEIU , OPC_J , OPC_BEQ ,   OPC_BNE , OPC_BLT , OPC_BLTU , OPC_BGE ,   OPC_BGEU , OPC_BGT , OPC_BGTU , OPC_BLE ,   OPC_BLEU , OPC_LI , OPC_LA , OPC_LW ,   OPC_SW , OPC_LW_G , OPC_SW_G , OPC_NOP ,   OPC_ECALL , OPC_EBREAK , OPC_CALL_EXIT_0 , OPC_CALL_READ_INT ,   OPC_CALL_PRINT_INT , OPC_CALL_PRINT_CHAR }

Functions
bool	isJumpInstruction (t_instruction *instr)
bool	isUnconditionalJump (t_instruction *instr)
bool	isExitInstruction (t_instruction *instr)
bool	isCallInstruction (t_instruction *instr)
t_regID	getSpillMachineRegister (int i)
t_listNode *	getListOfGenPurposeMachineRegisters (void)
t_listNode *	getListOfMachineRegisters (void)
t_listNode *	getListOfCallerSaveMachineRegisters (void)
void	doTargetSpecificTransformations (t_program *program)

Detailed Description

Definitions and functions to support the compilation target.

These functions and definitions allow the compiler to appropriately handle the target-specific semantics of some special instructions, included the instructions that are available to the ACSE intermediate representation but are not part of the target assembly language itself.

Macro Definition Documentation

NUM_GP_REGS

#define NUM_GP_REGS   23

Number of general-purpose registers usable by the register allocator.

Definition at line 37 of file target_info.h.

NUM_SPILL_REGS

#define NUM_SPILL_REGS   3

Number of registers available for spilled temporaries. Should be equal to the maximum number of unique register operands in a single instruction.

Definition at line 41 of file target_info.h.

TARGET_NAME

#define TARGET_NAME   "RISC-V_RV32IM"

Name of the target architecture.

Definition at line 27 of file target_info.h.

TARGET_PTR_GRANULARITY

#define TARGET_PTR_GRANULARITY   1

Number of bytes for each memory address.

Definition at line 30 of file target_info.h.

TARGET_REG_ZERO_IS_CONST

#define TARGET_REG_ZERO_IS_CONST   true

Defined to 'true' if the target has a 'zero' register whose value is always the constant zero.

Definition at line 34 of file target_info.h.

Typedef Documentation

t_regInt

typedef int32_t t_regInt

Signed data type with the same size of a target register.

Definition at line 24 of file target_info.h.

Enumeration Type Documentation

anonymous enum

anonymous enum

Opcode IDs used internally by ACSE to identify the various instructions.

Some opcodes are labeled "pseudo" if they need to be transformed to a sequence of other non-pseudo opcodes before emitting the output assembly file. Other pseudo opcodes are handled by the assembler, those are not marked as "pseudo" here.

Enumerator
OPC_ADD
OPC_SUB
OPC_AND
OPC_OR
OPC_XOR
OPC_MUL
OPC_DIV
OPC_REM
OPC_SLL
OPC_SRL
OPC_SRA
OPC_ADDI
OPC_SUBI
OPC_ANDI
OPC_ORI
OPC_XORI
OPC_MULI
OPC_DIVI
OPC_REMI
OPC_SLLI
OPC_SRLI
OPC_SRAI
OPC_SEQ
OPC_SNE
OPC_SLT
OPC_SLTU
OPC_SGE
OPC_SGEU
OPC_SGT
OPC_SGTU
OPC_SLE
OPC_SLEU
OPC_SEQI
OPC_SNEI
OPC_SLTI
OPC_SLTIU
OPC_SGEI
OPC_SGEIU
OPC_SGTI
OPC_SGTIU
OPC_SLEI
OPC_SLEIU
OPC_J
OPC_BEQ
OPC_BNE
OPC_BLT
OPC_BLTU
OPC_BGE
OPC_BGEU
OPC_BGT
OPC_BGTU
OPC_BLE
OPC_BLEU
OPC_LI
OPC_LA
OPC_LW
OPC_SW
OPC_LW_G
OPC_SW_G
OPC_NOP
OPC_ECALL
OPC_EBREAK
OPC_CALL_EXIT_0
OPC_CALL_READ_INT
OPC_CALL_PRINT_INT
OPC_CALL_PRINT_CHAR

Definition at line 86 of file target_info.h.

anonymous enum

anonymous enum

Machine register names.

Enumerator
REG_ZERO
REG_RA
REG_SP
REG_GP
REG_TP
REG_T0
REG_T1
REG_T2
REG_S0
REG_S1
REG_A0
REG_A1
REG_A2
REG_A3
REG_A4
REG_A5
REG_A6
REG_A7
REG_S2
REG_S3
REG_S4
REG_S5
REG_S6
REG_S7
REG_S8
REG_S9
REG_S10
REG_S11
REG_T3
REG_T4
REG_T5
REG_T6
NUM_REGISTERS

Definition at line 44 of file target_info.h.

Function Documentation

doTargetSpecificTransformations()

void doTargetSpecificTransformations

(

t_program *

program

)

Perform lowering of the program to a subset of the IR which can be represented as instructions of the target architecture.

Parameters

program

The program that needs to be transformed. The transformation is performed in-place.

Definition at line 349 of file target_transform.c.

getListOfCallerSaveMachineRegisters()

t_listNode * getListOfCallerSaveMachineRegisters

(

void

)

Retrieves the list of register IDs that can be modified by a given function call instruction, except for input and output parameters.

Returns

The list of register IDs stored inline as integers.

Definition at line 77 of file target_info.c.

getListOfGenPurposeMachineRegisters()

t_listNode * getListOfGenPurposeMachineRegisters

(

void

)

Retrieves the list of register IDs available for the register allocator, sorted in order of priority.

Returns

The list of register IDs stored inline as integers.

Definition at line 55 of file target_info.c.

getListOfMachineRegisters()

t_listNode * getListOfMachineRegisters

(

void

)

Retrieves the complete list of machine registers exception made for ones with a fixed value.

Returns

The list of register IDs stored inline as integers.

Definition at line 68 of file target_info.c.

getSpillMachineRegister()

t_regID getSpillMachineRegister

(

int

i

)

Retrieves a register ID suitable for spill operations. The maximum index is always bounded by NUM_SPILL_REGS.

Parameters

i	The index of the spill register to return, between 0 and NUM_SPILL_REGS (excluded).

Returns

The register ID of a machine register suitable for spilling.

Definition at line 48 of file target_info.c.

isCallInstruction()

bool isCallInstruction

(

t_instruction *

instr

)

Tests if the instruction is used to perform a function or system call.

Parameters

instr

The instruction to be examined.

Returns

true if the instruction is a call.

Definition at line 42 of file target_info.c.

isExitInstruction()

bool isExitInstruction

(

t_instruction *

instr

)

Tests if the instruction causes the program to exit.

Parameters

instr

The instruction to be examined.

Returns

true if the instruction exits the program.

Definition at line 9 of file target_info.c.

isJumpInstruction()

bool isJumpInstruction

(

t_instruction *

instr

)

Tests for jump/branch instructions.

Parameters

instr

The instruction to be examined.

Returns

true if the instruction is a jump/branch.

Definition at line 21 of file target_info.c.

isUnconditionalJump()

bool isUnconditionalJump

(

t_instruction *

instr

)

Tests for unconditional jump instructions.

Parameters

instr

The instruction to be examined.

Returns

true if the instruction is an unconditional jump.

Definition at line 15 of file target_info.c.